1. Field of the Invention
The present invention relates to a semiconductor wafer having dicing lines, and a semiconductor device obtained from the wafer.
2. Description of the Background Art
In the manufacture of a semiconductor device, an exposure process is performed a plurality of times. In the exposure process requiring high resolution and accuracy, a mask is aligned by a stepper, using an alignment mark for a stepper previously transferred on a semiconductor wafer. On the other hand, in the exposure process requiring little resolution and accuracy, the mask is aligned by a projection aligner (hereinafter referred to as "PJA"), using an alignment mark for a PJA previously transferred on the semiconductor wafer. In this way, using the stepper and the PJA properly brings improvements in cost and throughput. Thus, concurrent use of the stepper and the PJA has been prevalent. Now, we will give a description of the semiconductor wafer.
FIG. 7 shows a conceptual state of a conventional exposure process. In FIG. 7, R3 is a reticle with patterns CR31 of sixteen semiconductor element forming regions; D1 is a region other than the patterns CR31, corresponding to a dicing line D which will be described later; X is a lateral direction of a semiconductor wafer W; and Y is a longitudinal direction perpendicular to the lateral direction X. The number of shots on this semiconductor wafer W is 60.
The alignment mark for PJA requires a region corresponding to one or more reticles R3. In FIG. 7, two regions PM1 and PM2 have the alignment mark for PJA. Those regions are arranged in parallel to a plane portion of the edge of the semiconductor wafer W (facet).
FIG. 8 is a partial enlarged plan view of the semiconductor wafer W finally obtained through the exposure process in FIG. 7 and other processes. In FIG. 8, D is a dicing line extending straight in the lateral direction X or in the longitudinal direction Y in parallel to others; CR3 is a semiconductor element forming region with a semiconductor element, sectioned by the dicing lines D; SM1 and SM2 are alignment marks for a stepper; and TP is a TEG (Test Element Group) pattern.
The alignment marks SM1, SM2 and the TEG pattern TP are scattered over the dicing lines D which are unavailable regions other than the semiconductor element forming regions CR3 on the semiconductor wafer W.
The semiconductor element forming regions CR3 are all in the shape of a square each side of which is L1. That is, there is the same interval of L1 between adjacent dicing lines D (from edge to edge).
Using a dicing device (dicing saw), the semiconductor wafer W is sliced along the dicing lines D to obtain a plurality of chips. The longitudinal size of a chip is shown as L6.
The plurality of chips need to be the same in size. This is because chips of different sizes may not be easily mounted on a lead frame at a later assembly process or they may complicate a program of the dicing device.
Further, a blade of the dicing device needs to pass through the center of the dicing lines D. This is to prevent the blade of the dicing device from passing through the semiconductor element forming regions CR3 due to a mechanical error of the dicing device.
In order to achieve both, i.e., to equalize the chip size and to pass the blade through the center of the dicing lines, the dicing lines D both in the lateral direction X and in the longitudinal direction Y have had the same width Lb as shown in FIG. 8.
The dicing line is further disclosed in Japanese Patent Laid-Open No. P63-250119A in which every dicing line in the lateral direction has the same width and every dicing line in the longitudinal direction has the same width, but the former width is different from the latter.
The dicing lines, however, need to be wide enough to form the alignment marks SM1, SM2 and the TEG pattern TP thereon. As the width of the dicing lines D increases, an area of the unavailable regions other than the semiconductor element forming regions CR3 is increased on the semiconductor wafer W. This reduces the number of semiconductor element forming regions CR3 on the semiconductor wafer W, thereby reducing the number of chips obtained from the single semiconductor wafer W.